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CL(IDD): 19 cycles Row Cycle Time (tRCmin): 45.75ns(min.) Refresh to Active/Refresh Command Time (tRFCmin): 350ns(min.) Row Active Time (tRASmin): 32ns(min.) Maximum Operating Power: TBD W* UL Rating: 94 V – 0 Operating Temperature: 0o C to +85o C Storage Temperature: -55o C to +100o C
JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) Power Supply VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) 800MHz fCK for 1600Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 11, 10, 9, 8, 7, 6 Programmable Additive Latency: 0, CL – 2, or CL – 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS] Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C Asynchronous Reset PCB: Height 0.740” (18.75mm) or 1.180” (30.00mm)
JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) Power Supply VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) 800MHz fCK for 1600Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 11, 10, 9, 8, 7, 6, 5 Programmable Additive Latency: 0, CL – 2, or CL – 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS] Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C Asynchronous Reset PCB : Height 1.180” (30.00mm), single sided component
Power Supply: VDD = 1.2V Typical VDDQ = 1.2V Typical VPP = 2.5V Typical VDDSPD = 2.2V to 3.6V Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die VREFDQ generation and calibration Dual-rank On-board I2 serial presence-detect (SPD) EEPROM 16 internal banks; 4 groups of 4 banks each Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Fly-by topology Terminated control command and address bus PCB: Height 1.23” (31.25mm) RoHS Compliant and Halogen-Free
Power Supply: VDD=1.2V Typical VDDQ = 1.2V Typical VPP – 2.5V Typical VDDSPD=2.2V to 3.6V Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) Data bus inversion (DBI) for data bus On-die VREFDQ generation and calibration Dual-rank On-board I2 serial presence-detect (SPD) EEPROM 16 internal banks; 4 groups of 4 banks each Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Fly-by topology Terminated control command and address bus PCB: Height 1.23” (31.25mm) RoHS Compliant and Halogen-Free
JEDEC standard 1.5V (1.425V ~1.575V) Power Supply VDDQ = 1.5V (1.425V ~ 1.575V) 800MHz fCK for 1600Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 11, 10, 9, 8, 7, 6 Programmable Additive Latency: 0, CL – 2, or CL – 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS] Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C Asynchronous Reset PCB : Height 1.180” (30.00mm), double sided component